When developing electronic circuits, circuit analysis is often carried out in the design stage. The circuit analysis includes timing analysis, for example. The timing analysis involves simulating the circuit behavior, and verifying whether the circuit operates at the desired timing. By performing timing analysis, it is possible to detect timing errors due to wiring delay, for example, and to modify the circuit so as to prevent timing errors. As the size of the circuit increases, it becomes more difficult to design the circuit to satisfy the timing requirements. Accordingly, it is important to perform timing analysis and determine whether there is a timing error. For example, in the case of macros used in an ultrahigh-speed large-scale integration (LSI) having a clock frequency higher than several gigahertzes, timing analysis needs to be performed with very high accuracy. Note that the term “macro” as used herein refers to a functional circuit block of the LSI.
As a method of circuit timing analysis, simulation-based analysis is known that uses software called Simulation Program with Integrated Circuit Emphasis (SPICE), for example. With simulation using the software SPICE or the like, it is possible to perform timing analysis with high accuracy. However, it takes a considerable amount of time to perform accurate timing analysis. For example, as for extremely large mega macros, it is difficult to complete timing analysis within a practical length of time.
In view of the above, there has been proposed a method of performing simulation on a simplified circuit. For example, there has been proposed a technique of simplifying a large-scale load circuit by using a virtual control voltage source (see, for example, Japanese Laid-open Patent Publication No. 2006-146595).
There has also been proposed a technique of eliminating open ends of elements or eliminating nodes having no direct-current path so as to improve the analysis accuracy without needlessly increasing the processing load of circuit simulation. This technique removes, from among associated elements having open ends, every associated element all of whose terminals or all of whose terminals except one are open ends (see, for example, Japanese Laid-open Patent Publication No. 9-325982).
However, with the conventional technique of simplifying a circuit model, the accuracy of timing analysis might be reduced due to over-simplification of the circuit model. For instance, if every element all of whose terminals or all of whose terminals except one are open ends is removed, even an element that greatly affects the timing analysis might be removed. If an element that greatly affects the timing analysis is removed, an error corresponding to the degree that the element affects the operation timing of the actual circuit might occur in the results of the timing analysis. Thus, the analysis accuracy is reduced.
The problem of reduced analysis accuracy due to over-simplification of the circuit model occurs not only in timing analysis, but also in other analyses.